Mobile telephone technology has greatly advanced in recent years, as evident by the higher performance digital mobile telephones now available. To a large extent, these advances stem from the widespread deployment of modern digital wireless modulation technologies, such as time division multiple access (TDMA), code division multiple access (CDMA) technologies including conventional CDMA, wideband CDMA (WCDMA) and CDMA2000 standards and personal communications service (PCS) modulation. The carrier frequencies for these modulated signals ranges from on the order of 800 MHz to as high as 2.0 GHz. These and other digital modulation and communications techniques have greatly improved wireless telephone services, at reduced cost to the consumer. All of the aforementioned technologies require that signals be converted from analog to digital form.
An analog input signal can be converted into a digital output word using an analog-to-digital converter (ADC), which contains a mixture of analog and digital circuitry. The speed, resolution and linearity of the conversion affect the accuracy with which the digital output word represents the analog input signal. The conversion speed must be high enough to sample the shortest analog input signal period (highest analog signal frequency) at least twice. The number of bits in the digital output word determines the conversion resolution and has to be large enough to resolve the maximum peak-to-peak analog input signal into a required degree of granularity. The conversion linearity has to be sufficient to operate at or preferably below a required maximum level of distortion associated with the conversion process.
Several different algorithms and architectures exist that may be employed to accomplish a conversion. These include delta-sigma, successive approximation, pipeline and flash ADCs in increasing order of bandwidth capability but typically decreasing order of resolution capability. Of particular interest is the delta-sigma ADC, which typically provides a reasonable trade-off between sampling rate and bits of resolution while providing a low component count that benefits cost of production, size and reliability.
The delta-sigma (or sigma-delta) ADC employs delta-sigma modulation techniques that digitize an input signal using very low resolution (one-bit) and a very high sampling rate (often in the megahertz range). Oversampling and the use of digital filters increases the resolution to as many as twenty or more bits. It is especially useful for high resolution conversion of low to moderate frequency signals as well as low distortion conversion of signals containing audio frequencies due to its inherent qualities of good linearity and high accuracy.
Delta-sigma ADCs may operate in discrete time or continuous time. In either case, the delta-sigma ADC employs an input modulator and an output digital filter and decimator. The input modulator operates by accepting an input signal through an input summing junction, which feeds a loop filter. The loop filter basically provides an integrated value of this signal to a quantizer, which is typically implemented as a comparator. The quantizer output signal is fed back to the input summing junction through a circuit that acts as a one-bit digital-to-analog converter (DAC). This feedback loop forces the average of the feedback signal to be substantially equal to the input signal. The number of feedback loops in the loop filter (which is the same as the number of integrators) determines the order of the delta-sigma ADC. In the case of a one-bit quantizer, the density of “ones” in the quantizer output signal is proportional to the value of the input signal. The input modulator oversamples the input signal by clocking the comparator at a rate that is much higher than the Nyquist rate. Then, the output digital filter and decimator produce output data words at a data rate appropriate to the conversion.
Without careful optimization, existing discrete-time second-order order delta-sigma ADC designs that employ an amplifier in each integrator (a total of two amplifiers) often consume excessive integrated circuit (IC) chip area and power. Careful optimization can be time consuming and may require a mature process technology that has been thoroughly characterized. Reducing the number of amplifiers can result in reduced chip area and power consumption. Unfortunately, existing discrete-time second-order order delta-sigma ADC designs that employ fewer than two amplifiers are often vulnerable to real-world operating conditions, or “non-idealities,” such as mismatch, noise and non-linearity.
One existing discrete-time second-order order delta-sigma ADC design is the passive delta-sigma modulation (PDSM) ADC (see, e.g., Chen, et al., “A 0.25 mW 13-bit passive SD modulator for a 10 MHz IF input,” in ISSCC Dig. Tech. Papers, February 1996; and Chen, et al., “A 1.5V 1 mA 80 dB Passive SD ADC in 0.13 mm Digital CMOS Process,” in ISSCC Dig. Tech. Papers, February 2003). PSDM ADCs are subject to comparator offset and flicker-noise and excess delay in the feedback loop. Comparator offset and flicker-noise are typically reduced using offset storage cancellation, chopping or correlated double-sampling. Thermal noise must also be reduced, resulting in large high-current preamplifiers. Offset reduction techniques can consume too much power and area. Further, the timing the offset reduction techniques require may limit the maximum sample rate (Fs). Excess loop delay is avoided by requiring each preamplifier 3 dB-bandwidth to be greater than Fs. Then, the feedback delay must be fixed and less than or equal to half of the sample period (Ts=1/Fs).
Another existing discrete-time second-order order delta-sigma ADC design is the active-passive delta-sigma modulation (APDSM) ADC (see, e.g., U.S. Patent Publication No. 20050116850, “Continuous Time Fourth Order Delta Sigma Analog-to-Digital Converter;” and Das, et al., “A 4th-order 86 dB CT SD ADC with Two Amplifiers in 90 nm CMOS,” in ISSCC Dig. Tech. Papers, February 2005). APSDM ADCs are subject to resistor and capacitor absolute value variances and excess loop delay and parasitic poles. Variances in resistor and capacitor absolute value tend to cause large absolute ADC gain variations and the movement of poles and zeros, which degrades performance and stability. Counteracting these vulnerabilities requires extra circuitry to control the reference voltage so that the absolute gain of the ADC does not vary substantially, typically less than ±1 dB. Without this circuitry, the absolute gain may vary by as much as ±6 dB. Excess loop delay and parasitic poles vulnerabilities require the amplifier, comparator, and DAC to meet delay requirements over an expected range of Fs. The feedback delay must be fixed and less than or equal to half of Ts. Further, a loop delay compensation circuit may be required to reduce sensitivity to quantizer metastability, latch clock-to-Q time, and feedback DAC propagation delay.
Both PSDM and APSDM ADCs may require that the input common mode voltage be level-shifted for proper operation and reliability. This requires additional circuits for level-shifting, which consume additional chip area and power.
Yet another existing discrete-time second-order order delta-sigma ADC design is the single-amplifier delta-sigma modulation (SASD) ADC (see, e.g., U.S. Patent Publication No. 20040169596, “Higher Order Delta-sigma Analog-to-Digital Converter Based on Finite Impulse Response Filter;” and Koh, et al., “A 66 dB DR 1.2V 1.2 mW Single-Amplifier Double-Sampling second-order SD ADC for WCDMA in 90 nm CMOS” in ISSCC Dig. Tech. Papers, February 2005). SASD ADCs are subject to non-idealities in the linearity of amplification and gain, DC offset, limits on DC gain, gain-bandwidth product and slew rate, high input referred noise and sensitivity to capacitor mismatch, a data-dependent offset at the amplifier input in cases involving double sampling and increased total harmonic distortion. All of these can cause high-frequency noise to fold into the signal band and ultimately limit the achievable signal-to-noise ratio (SNR) and signal to noise-plus-distortion ratio (SNDR).